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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-28 13:06:34 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2019-07-08 14:52:54 +0000 |
commit | 92185e373ea70b4a9af6fb7f38b0855d7d898bf3 (patch) | |
tree | 793009940a0058c4ea4435aa8ed1013bd9dff438 /src/southbridge/intel/common/spi.h | |
parent | 3fcea0dfadde89fd425bcaaecdd357e0d10caf87 (diff) | |
download | coreboot-92185e373ea70b4a9af6fb7f38b0855d7d898bf3.tar.xz |
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu,
with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/common/spi.h')
-rw-r--r-- | src/southbridge/intel/common/spi.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h new file mode 100644 index 0000000000..3b8410cd9f --- /dev/null +++ b/src/southbridge/intel/common/spi.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_SPI_H +#define SOUTHBRIDGE_INTEL_SPI_H + +enum optype { + READ_NO_ADDR = 0, + WRITE_NO_ADDR = 1, + READ_WITH_ADDR = 2, + WRITE_WITH_ADDR = 3 +}; + +struct intel_spi_op { + u8 op; + enum optype type; +}; + +struct intel_swseq_spi_config { + u8 opprefixes[2]; + struct intel_spi_op ops[8]; +}; + +void spi_finalize_ops(void); +void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config); + +#endif |