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authorNico Huber <nico.h@gmx.de>2018-06-05 22:58:20 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-11 08:44:02 +0000
commit3b7668325b6a891d2382c360cf41e64f662256c9 (patch)
treea9afeeb428926abc6e61d4096f8e2017fddc32a6 /src/southbridge/intel/common
parent9e53db4dc32da0aae986e4813401d5a92c2bb0fd (diff)
downloadcoreboot-3b7668325b6a891d2382c360cf41e64f662256c9.tar.xz
sb/intel/common: Include SPI driver into postcar stage
Change-Id: I2ea07cdeb8fc70dbf516831f4da5949fef136b37 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common')
-rw-r--r--src/southbridge/intel/common/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 2a0bca62f5..bf3a86e8ff 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -29,6 +29,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
+postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
ifeq ($(CONFIG_SPI_FLASH_SMM),y)
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c