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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-08 19:01:30 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-26 09:14:27 +0000 |
| commit | 3c18186e76c0e27590f54c3ae39c7b951ac28749 (patch) | |
| tree | 00ee1696f7701337353529e54a30e63a42f4de36 /src/southbridge/intel/common | |
| parent | 22236a580d45bdd6d7b5f9d2d64f3ddf64f4dd04 (diff) | |
| download | coreboot-3c18186e76c0e27590f54c3ae39c7b951ac28749.tar.xz | |
sb,soc/intel: Refactor power_on_after_fail option
It's only necessary to call get_option() with SLP_TYP S5.
Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/smihandler.c | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 18f171dd1f..4279eb88d7 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -93,14 +93,11 @@ __weak void southbridge_smm_xhci_sleep(u8 slp_type) { } -static void southbridge_smi_sleep(void) +static int power_on_after_fail(void) { - u8 reg8; - u32 reg32; - u8 slp_typ; u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - // save and recover RTC port values + /* save and recover RTC port values */ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); @@ -108,6 +105,15 @@ static void southbridge_smi_sleep(void) outb(tmp70, 0x70); outb(tmp72, 0x72); + /* For "KEEP", switch to "OFF" - KEEP is software emulated. */ + return (s5pwr == MAINBOARD_POWER_ON); +} + +static void southbridge_smi_sleep(void) +{ + u32 reg32; + u8 slp_typ; + /* First, disable further SMIs */ write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN); @@ -153,16 +159,11 @@ static void southbridge_smi_sleep(void) write_pmbase32(GPE0_EN, 0); - /* Always set the flag in case CMOS was changed on runtime. For - * "KEEP", switch to "OFF" - KEEP is software emulated - */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - pci_write_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, reg8); + /* Always set the flag in case CMOS was changed on runtime. */ + if (power_on_after_fail()) + pci_and_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, ~1); + else + pci_or_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, 1); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); |