summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/common
diff options
context:
space:
mode:
authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-09-14 10:16:40 -0600
committerMartin Roth <martinroth@google.com>2018-09-19 16:30:04 +0000
commit638bd13a656e9bbf077d2ab3d707ea09e715d388 (patch)
tree629d3e9cf093b8ff87ac04103f9a441e5362eb2e /src/southbridge/intel/common
parent892af1801f01adfebe97a63200bcc8d1b36e88ba (diff)
downloadcoreboot-638bd13a656e9bbf077d2ab3d707ea09e715d388.tar.xz
amd/stoneyridge: Sync PSP base to MSR
According to AMD, there exists an undocumented MSR which must be written with the PSP's base address. Read the value from the PSP's config space and sync each core's copy of the MSR to match. BUG=b:76167350 TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28608 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common')
0 files changed, 0 insertions, 0 deletions