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| author | Peter Lemenkov <lemenkov@gmail.com> | 2018-10-23 11:12:46 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 11:56:38 +0000 |
| commit | 7b42811fa55bb5ea67c8dc71cd9436cd8ddd83c3 (patch) | |
| tree | 94dd4dcd1d56127b41b37603c3ef491850b969f5 /src/southbridge/intel/common | |
| parent | aa6d38859768486d3353edd7aef092b6318ac1bf (diff) | |
| download | coreboot-7b42811fa55bb5ea67c8dc71cd9436cd8ddd83c3.tar.xz | |
sb/intel: Use common RCBA MACROs
This commit follows up on commit 2e464cf3 with Change-Id
I61fb3b01ff15ba2da2ee938addfa630c282c9870.
Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/rcba.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index b6cba8ea5f..e7482f9bdb 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -18,12 +18,12 @@ #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H #ifndef __ACPI__ + #define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif -#ifndef __ACPI__ +/* Root Complex Register Block */ +#define RCBA 0xf0 +#define RCBA_ENABLE 0x01 #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) @@ -36,6 +36,10 @@ #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) +#else + +#define DEFAULT_RCBA 0xfed1c000 #endif /* __ACPI__ */ + #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ |