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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-30 13:23:32 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-07 12:35:42 +0000 |
| commit | 6683e409d3688217e70f1f19deab152790b0f495 (patch) | |
| tree | 965070f130e9b367631c746ab219aa73f3569238 /src/southbridge/intel/common | |
| parent | d1a0c5770803e45dabecf6094fccb9895ea76d10 (diff) | |
| download | coreboot-6683e409d3688217e70f1f19deab152790b0f495.tar.xz | |
usbdebug: Refactor early enable
Always sanity check for EHCI class device and move
PCI function power enablement up.
Change-Id: I1eebe813fbb420738af2d572178213fc660f392a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/usb_debug.c | 28 |
1 files changed, 7 insertions, 21 deletions
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index e1cd6575d0..f74da657fd 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -27,27 +27,20 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) u32 class; pci_devfn_t dev; -#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS) + if (!IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)) + return PCI_DEV(0, 0x1d, 7); + if (hcd_idx==2) dev = PCI_DEV(0, 0x1a, 0); else dev = PCI_DEV(0, 0x1d, 0); -#else - dev = PCI_DEV(0, 0x1d, 7); -#endif + /* If we enter here before RCBA programming, EHCI function may + * appear with the highest function number instead. + */ class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; -#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS) - if (class != PCI_EHCI_CLASSCODE) { - /* If we enter here before RCBA programming, EHCI function may - * appear with the highest function number instead. - */ - dev |= PCI_DEV(0, 0, 7); - class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; - } -#endif if (class != PCI_EHCI_CLASSCODE) - return 0; + dev |= PCI_DEV(0, 0, 7); return dev; } @@ -57,10 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ - /* Bail out. No console to complain in. */ - if (!dev) - return; -} |