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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-07 12:44:00 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-28 10:34:43 +0000
commit7ba14406c30f90cebde9f539f1987348cfc998e4 (patch)
treee3ead89f5e263ff9edeb0855df13c6722e64db35 /src/southbridge/intel/common
parent17387f67ad0d286332e4c498de08354a37e61fdb (diff)
downloadcoreboot-7ba14406c30f90cebde9f539f1987348cfc998e4.tar.xz
intel/spi: Switch to native PCI config accessors
Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common')
-rw-r--r--src/southbridge/intel/common/spi.c37
1 files changed, 4 insertions, 33 deletions
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 60c0b8dd6e..1d871d2c5d 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -24,6 +24,7 @@
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
+#include <device/device.h>
#include <device/pci.h>
#include <spi_flash.h>
@@ -34,36 +35,6 @@
#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
-
-#ifdef __SMM__
-#define pci_read_config_byte(dev, reg, targ)\
- *(targ) = pci_read_config8(dev, reg)
-#define pci_read_config_word(dev, reg, targ)\
- *(targ) = pci_read_config16(dev, reg)
-#define pci_read_config_dword(dev, reg, targ)\
- *(targ) = pci_read_config32(dev, reg)
-#define pci_write_config_byte(dev, reg, val)\
- pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
- pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
- pci_write_config32(dev, reg, val)
-#else /* !__SMM__ */
-#include <device/device.h>
-#define pci_read_config_byte(dev, reg, targ)\
- *(targ) = pci_read_config8(dev, reg)
-#define pci_read_config_word(dev, reg, targ)\
- *(targ) = pci_read_config16(dev, reg)
-#define pci_read_config_dword(dev, reg, targ)\
- *(targ) = pci_read_config32(dev, reg)
-#define pci_write_config_byte(dev, reg, val)\
- pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
- pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
- pci_write_config32(dev, reg, val)
-#endif /* !__SMM__ */
-
static int spi_is_multichip(void);
typedef struct spi_slave ich_spi_slave;
@@ -308,7 +279,7 @@ void spi_init(void)
struct device *dev = pcidev_on_root(31, 0);
#endif
- pci_read_config_dword(dev, 0xf0, &rcba);
+ rcba = pci_read_config32(dev, 0xf0);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {
@@ -356,10 +327,10 @@ void spi_init(void)
ich_set_bbar(0);
/* Disable the BIOS write protect so write commands are allowed. */
- pci_read_config_byte(dev, 0xdc, &bios_cntl);
+ bios_cntl = pci_read_config8(dev, 0xdc);
/* Deassert SMM BIOS Write Protect Disable. */
bios_cntl &= ~(1 << 5);
- pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
+ pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
}
static void spi_init_cb(void *unused)