diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-08-15 16:27:06 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-08-29 18:36:20 +0200 |
| commit | 8101aa6bb02c586cd0d1ab2cf99148329319aaf9 (patch) | |
| tree | 5609cabef4a330fa5438c74c749f763c39565693 /src/southbridge/intel/common | |
| parent | 24100100181bd770ce0f1181a1770a0808790cde (diff) | |
| download | coreboot-8101aa6bb02c586cd0d1ab2cf99148329319aaf9.tar.xz | |
usbdebug: Support choice of EHCI controller
Nowadays, chipsets or boards do not only have one USB port with the
capabilities of a debug port but several ones. Some of these ports are
easier accessible than others, so making them configurable is also necessary.
This change adds infrastructure to switch between EHCI controllers,
but does not implement it for any chipset.
Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3438
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/usb_debug.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 6b934f4fa0..3fed2ab854 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -26,25 +26,29 @@ #include <usbdebug.h> #include <device/pci_def.h> +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x1d, 7); +} + /* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { u32 dbgctl; - pci_devfn_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Force ownership of the Debug Port to the EHCI controller. */ - dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); + dbgctl = read32(base + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); - write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); + write32(base + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); } |