diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-16 18:31:34 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-16 18:31:34 +0000 |
commit | 0401bd89b6e7105ca597a221fdbe2a8b75c35296 (patch) | |
tree | ec342f9dcaae2619bcb06a57789a07328402ea71 /src/southbridge/intel/esb6300/esb6300_pic.c | |
parent | 9fe4d797a37671a65053add3f7cca27397db0b9b (diff) | |
download | coreboot-0401bd89b6e7105ca597a221fdbe2a8b75c35296.tar.xz |
coreboot has 13 instances of IOAPIC setup distributed across a lot
of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/esb6300/esb6300_pic.c')
-rw-r--r-- | src/southbridge/intel/esb6300/esb6300_pic.c | 45 |
1 files changed, 2 insertions, 43 deletions
diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c index 97635ae524..9d02536cd4 100644 --- a/src/southbridge/intel/esb6300/esb6300_pic.c +++ b/src/southbridge/intel/esb6300/esb6300_pic.c @@ -6,50 +6,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <arch/ioapic.h> #include "esb6300.h" -#define ALL (0xff << 24) -#define NONE (0) -#define DISABLED (1 << 16) -#define ENABLED (0 << 16) -#define TRIGGER_EDGE (0 << 15) -#define TRIGGER_LEVEL (1 << 15) -#define POLARITY_HIGH (0 << 13) -#define POLARITY_LOW (1 << 13) -#define PHYSICAL_DEST (0 << 11) -#define LOGICAL_DEST (1 << 11) -#define ExtINT (7 << 8) -#define NMI (4 << 8) -#define SMI (2 << 8) -#define INT (1 << 8) - -static void setup_ioapic(device_t dev) -{ - int i; - unsigned long value_low, value_high; - unsigned long ioapic_base = 0xfec10000; - volatile unsigned long *l; - unsigned interrupts; - - l = (unsigned long *) ioapic_base; - - l[0] = 0x01; - interrupts = (l[04] >> 16) & 0xff; - for (i = 0; i < interrupts; i++) { - l[0] = (i * 2) + 0x10; - l[4] = DISABLED; - value_low = l[4]; - l[0] = (i * 2) + 0x11; - l[4] = NONE; /* Should this be an address? */ - value_high = l[4]; - if (value_low == 0xffffffff) { - printk_warning("%s IO APIC not responding.\n", - dev_path(dev)); - return; - } - } -} - static void pic_init(struct device *dev) { @@ -64,7 +23,7 @@ static void pic_init(struct device *dev) pci_write_config8(dev, 0x3c, 0xff); /* Setup the ioapic */ - setup_ioapic(dev); + clear_ioapic(0xfec10000); } static void pic_read_resources(device_t dev) |