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author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-12 17:34:08 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-12 17:34:08 +0000 |
commit | 74d1a6e8a166cd477f667a6fcb1e96b8a0cbdac1 (patch) | |
tree | 9cbdbe86bd282da60bfcbef7108ca6790bcde94e /src/southbridge/intel/esb6300 | |
parent | 4ffde94c4ec51cdb24103ec13653e6f40513e1bb (diff) | |
download | coreboot-74d1a6e8a166cd477f667a6fcb1e96b8a0cbdac1.tar.xz |
We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/esb6300')
-rw-r--r-- | src/southbridge/intel/esb6300/esb6300_lpc.c | 4 | ||||
-rw-r--r-- | src/southbridge/intel/esb6300/esb6300_pic.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c index 9a48e05303..67bcadc961 100644 --- a/src/southbridge/intel/esb6300/esb6300_lpc.c +++ b/src/southbridge/intel/esb6300/esb6300_lpc.c @@ -242,7 +242,7 @@ static void lpc_init(struct device *dev) value |= (1 << 8)|(1<<7); value |= (6 << 0)|(1<<13)|(1<<11); pci_write_config32(dev, 0xd0, value); - setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID + setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID /* disable reset timer */ pci_write_config8(dev, 0xd4, 0x02); @@ -330,7 +330,7 @@ static void esb6300_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c index 5bbf317411..b9bfdf1fe3 100644 --- a/src/southbridge/intel/esb6300/esb6300_pic.c +++ b/src/southbridge/intel/esb6300/esb6300_pic.c @@ -23,7 +23,7 @@ static void pic_init(struct device *dev) pci_write_config8(dev, 0x3c, 0xff); /* Setup the ioapic */ - clear_ioapic(0xfec10000); + clear_ioapic(IO_APIC_ADDR + 0x10000); } static void pic_read_resources(device_t dev) @@ -35,7 +35,7 @@ static void pic_read_resources(device_t dev) /* Report the pic1 mbar resource */ res = new_resource(dev, 0x44); - res->base = 0xfec10000; + res->base = IO_APIC_ADDR + 0x10000; res->size = 256; res->limit = res->base + res->size -1; res->align = 8; |