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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-02-09 19:21:30 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-02-16 20:10:54 +0100 |
| commit | 6f6a249a75927476ba5e06bb2b0a0138e0cf63ea (patch) | |
| tree | 81c789db2e93396738929c9bb3b26b84771135b6 /src/southbridge/intel/fsp_bd82x6x | |
| parent | 6e56de3d202c2175a13c91ab2c1bc1eb0d7f652a (diff) | |
| download | coreboot-6f6a249a75927476ba5e06bb2b0a0138e0cf63ea.tar.xz | |
usbdebug: Remove EHCI_DEBUG_OFFSET
Read this variable from PCI configuration capabilities list instead.
Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/Kconfig | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index 1a8e80ac07..b2b4929348 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -37,10 +37,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/fsp_bd82x6x/bootblock.c" |