southbridge/intel: Add FSP based i89xx southbridge support

The Intel i89xx is a communications chipset that pairs with
Sandy(Ivy)bridge processors. It has a lot in common with
the bd82x6x chipset, but fewer devices and options.

Change-Id: I11bcd1edc80f72a1b2521def9be0d1bde5789a79
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12166
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 80 insertions, 0 deletions

diff --git a/src/southbridge/intel/fsp_i89xx/bootblock.c b/src/southbridge/intel/fsp_i89xx/bootblock.c
new file mode 100644
index 0000000000..0e6465c0cd
--- /dev/null
+++ b/src/southbridge/intel/fsp_i89xx/bootblock.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <cpu/x86/tsc.h>
+#include "pch.h"
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(void)
+{
+	u8 reg8;
+	pci_devfn_t dev;
+
+	dev = PCI_DEV(0, 0x1f, 0);
+
+	reg8 = pci_read_config8(dev, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(void)
+{
+	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+
+	/* Enable port 80 POST on LPC */
+	pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+	volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
+	u32 reg32 = *gcs;
+	reg32 = reg32 & ~0x04;
+	*gcs = reg32;
+}
+
+static void set_spi_speed(void)
+{
+	u32 fdod;
+	u8 ssfc;
+
+	/* Observe SPI Descriptor Component Section 0 */
+	RCBA32(0x38b0) = 0x1000;
+
+	/* Extract the Write/Erase SPI Frequency from descriptor */
+	fdod = RCBA32(0x38b4);
+	fdod >>= 24;
+	fdod &= 7;
+
+	/* Set Software Sequence frequency to match */
+	ssfc = RCBA8(0x3893);
+	ssfc &= ~7;
+	ssfc |= fdod;
+	RCBA8(0x3893) = ssfc;
+}
+
+static void bootblock_southbridge_init(void)
+{
+	enable_spi_prefetch();
+	enable_port80_on_lpc();
+	set_spi_speed();
+
+	/* Enable upper 128bytes of CMOS */
+	RCBA32(RC) = (1 << 2);
+}