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authorArthur Heymans <arthur@aheymans.xyz>2017-04-12 17:01:31 +0200
committerMartin Roth <martinroth@google.com>2017-08-06 23:26:15 +0000
commit16fe79048f5254661ff2342aa481cbb44657b7ff (patch)
tree5ad72bc5c5a97ca9a7a47f5ab24bbe622f12e9e9 /src/southbridge/intel/fsp_i89xx
parent12d010306b3892b01350e96d83275206215d9f31 (diff)
downloadcoreboot-16fe79048f5254661ff2342aa481cbb44657b7ff.tar.xz
sb/intel/*: Use common SMBus functions
All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_i89xx')
-rw-r--r--src/southbridge/intel/fsp_i89xx/Kconfig2
-rw-r--r--src/southbridge/intel/fsp_i89xx/early_smbus.c2
-rw-r--r--src/southbridge/intel/fsp_i89xx/pch.h16
-rw-r--r--src/southbridge/intel/fsp_i89xx/smbus.h91
4 files changed, 3 insertions, 108 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig
index 9dfbbf7169..67c2665e66 100644
--- a/src/southbridge/intel/fsp_i89xx/Kconfig
+++ b/src/southbridge/intel/fsp_i89xx/Kconfig
@@ -32,6 +32,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select COMMON_FADT
select HAVE_INTEL_FIRMWARE
select NO_EARLY_BOOTBLOCK_POSTCODES
+ select SOUTHBRIDGE_INTEL_COMMON
+ select SOUTHBRIDGE_INTEL_COMMON_SMBUS
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/fsp_i89xx/early_smbus.c b/src/southbridge/intel/fsp_i89xx/early_smbus.c
index 0d41d5eaf2..1451179915 100644
--- a/src/southbridge/intel/fsp_i89xx/early_smbus.c
+++ b/src/southbridge/intel/fsp_i89xx/early_smbus.c
@@ -19,8 +19,8 @@
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
+#include <southbridge/intel/common/smbus.h>
#include "pch.h"
-#include "smbus.h"
void enable_smbus(void)
{
diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h
index 9ae9467a7a..447178865c 100644
--- a/src/southbridge/intel/fsp_i89xx/pch.h
+++ b/src/southbridge/intel/fsp_i89xx/pch.h
@@ -174,22 +174,6 @@ void early_pch_init(void);
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
-/* SMBus I/O bits. */
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL 0x2
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
-
-#define SMBUS_TIMEOUT (10 * 1000 * 100)
-
-
/* Southbridge IO BARs */
#define GPIOBASE 0x48
diff --git a/src/southbridge/intel/fsp_i89xx/smbus.h b/src/southbridge/intel/fsp_i89xx/smbus.h
deleted file mode 100644
index 92b05b78c2..0000000000
--- a/src/southbridge/intel/fsp_i89xx/smbus.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/smbus_def.h>
-#include "pch.h"
-#include <delay.h>
-
-static int smbus_wait_until_ready(u16 smbus_base)
-{
- unsigned loops = SMBUS_TIMEOUT;
- unsigned char byte;
- do {
- udelay(1);
- if (--loops == 0)
- break;
- byte = inb(smbus_base + SMBHSTSTAT);
- } while (byte & 1);
- return loops ? 0 : -1;
-}
-
-static int smbus_wait_until_done(u16 smbus_base)
-{
- unsigned loops = SMBUS_TIMEOUT;
- unsigned char byte;
- do {
- udelay(1);
- if (--loops == 0)
- break;
- byte = inb(smbus_base + SMBHSTSTAT);
- } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
- return loops ? 0 : -1;
-}
-
-static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
-{
- unsigned char global_status_register;
- unsigned char byte;
-
- if (smbus_wait_until_ready(smbus_base) < 0) {
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
- /* Setup transaction */
- /* Disable interrupts */
- outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
- /* Set the device I'm talking too */
- outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
- /* Set the command/address... */
- outb(address & 0xff, smbus_base + SMBHSTCMD);
- /* Set up for a byte data read */
- outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
- (smbus_base + SMBHSTCTL));
- /* Clear any lingering errors, so the transaction will run */
- outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
-
- /* Clear the data byte... */
- outb(0, smbus_base + SMBHSTDAT0);
-
- /* Start the command */
- outb((inb(smbus_base + SMBHSTCTL) | 0x40),
- smbus_base + SMBHSTCTL);
-
- /* Poll for transaction completion */
- if (smbus_wait_until_done(smbus_base) < 0) {
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
-
- global_status_register = inb(smbus_base + SMBHSTSTAT);
-
- /* Ignore the "In Use" status... */
- global_status_register &= ~(3 << 5);
-
- /* Read results of transaction */
- byte = inb(smbus_base + SMBHSTDAT0);
- if (global_status_register != (1 << 1)) {
- return SMBUS_ERROR;
- }
- return byte;
-}