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author | Martin Roth <martinroth@google.com> | 2015-10-11 10:36:26 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2015-10-14 22:49:03 +0000 |
commit | 58562405c8c416a415652516b8af31b204b4ff0d (patch) | |
tree | 3311f3f5feceea80a048337f0485fc9c956ee5ac /src/southbridge/intel/fsp_rangeley/Makefile.inc | |
parent | 83e4c5613eecc5283d9a66997dc90e26384f9284 (diff) | |
download | coreboot-58562405c8c416a415652516b8af31b204b4ff0d.tar.xz |
Revert "Remove FSP Rangeley SOC and mohonpeak board support"
This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763c16688d43752adbae2c76e7764da45.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/Makefile.inc')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/Makefile.inc | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc new file mode 100644 index 0000000000..2a66b90ec8 --- /dev/null +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) + +ramstage-y += soc.c +ramstage-y += lpc.c +ramstage-y += sata.c +ramstage-y += reset.c +ramstage-y += watchdog.c +ramstage-y += spi.c +ramstage-y += smbus.c +ramstage-y += acpi.c + +romstage-y += early_usb.c early_smbus.c gpio.c reset.c early_spi.c early_init.c +romstage-y += romstage.c + +romstage-$(CONFIG_USBDEBUG) += usb_debug.c +ramstage-$(CONFIG_USBDEBUG) += usb_debug.c + +endif |