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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:37:28 +0100 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:45 +0000 |
commit | c2c634a089fa990418c363e2ff2e5ff70bdd3580 (patch) | |
tree | 042e376cee473f72f143ed76768f50536ab323ef /src/southbridge/intel/fsp_rangeley/Makefile.inc | |
parent | 298619f6d9adde49b4279c906b0d20a41f919a61 (diff) | |
download | coreboot-c2c634a089fa990418c363e2ff2e5ff70bdd3580.tar.xz |
nb/sb/cpu: Drop Intel Rangeley support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I41589118579988617677cf48af5401bc35b23e05
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/Makefile.inc')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/Makefile.inc | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc deleted file mode 100644 index 67a51af15a..0000000000 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ /dev/null @@ -1,33 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Google Inc. -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) - -ramstage-y += soc.c -ramstage-y += lpc.c -ramstage-y += sata.c -ramstage-y += spi.c -ramstage-y += smbus.c -ramstage-y += acpi.c - -romstage-y += early_usb.c early_smbus.c gpio.c early_init.c -romstage-y += romstage.c - -bootblock-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c - -endif |