diff options
author | Martin Roth <martinroth@google.com> | 2015-10-11 10:36:26 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2015-10-14 22:49:03 +0000 |
commit | 58562405c8c416a415652516b8af31b204b4ff0d (patch) | |
tree | 3311f3f5feceea80a048337f0485fc9c956ee5ac /src/southbridge/intel/fsp_rangeley/gpio.h | |
parent | 83e4c5613eecc5283d9a66997dc90e26384f9284 (diff) | |
download | coreboot-58562405c8c416a415652516b8af31b204b4ff0d.tar.xz |
Revert "Remove FSP Rangeley SOC and mohonpeak board support"
This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763c16688d43752adbae2c76e7764da45.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/gpio.h')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/gpio.h | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h new file mode 100644 index 0000000000..0ead65cb40 --- /dev/null +++ b/src/southbridge/intel/fsp_rangeley/gpio.h @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef INTEL_RANGELEY_GPIO_H +#define INTEL_RANGELEY_GPIO_H + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 +#define GPIO_MODE_NONE 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_TPE_DISABLE 0 +#define GPIO_TPE_ENABLE 1 + +#define GPIO_TNE_DISABLE 0 +#define GPIO_TNE_ENABLE 1 + +#define GPIO_TS_DISABLE 0 +#define GPIO_TS_ENABLE 1 + +#define GPIO_WE_DISABLE 0 +#define GPIO_WE_ENABLE 1 + +struct soc_gpio { + u32 gpio0 : 1; + u32 gpio1 : 1; + u32 gpio2 : 1; + u32 gpio3 : 1; + u32 gpio4 : 1; + u32 gpio5 : 1; + u32 gpio6 : 1; + u32 gpio7 : 1; + u32 gpio8 : 1; + u32 gpio9 : 1; + u32 gpio10 : 1; + u32 gpio11 : 1; + u32 gpio12 : 1; + u32 gpio13 : 1; + u32 gpio14 : 1; + u32 gpio15 : 1; + u32 gpio16 : 1; + u32 gpio17 : 1; + u32 gpio18 : 1; + u32 gpio19 : 1; + u32 gpio20 : 1; + u32 gpio21 : 1; + u32 gpio22 : 1; + u32 gpio23 : 1; + u32 gpio24 : 1; + u32 gpio25 : 1; + u32 gpio26 : 1; + u32 gpio27 : 1; + u32 gpio28 : 1; + u32 gpio29 : 1; + u32 gpio30 : 1; + u32 gpio31 : 1; +} __attribute__ ((packed)); + +struct soc_cfio { + u32 pad_conf_0; + u32 pad_conf_1; + u32 pad_val; + u32 pad_dft; +} __attribute__ ((packed)); + +struct soc_gpio_map { + /* GPIO core */ + struct { + const struct soc_gpio *mode; + const struct soc_gpio *direction; + const struct soc_gpio *level; + const struct soc_gpio *tpe; + const struct soc_gpio *tne; + const struct soc_gpio *ts; + const struct soc_cfio *cfio_init; + const u32 cfio_entrynum; + }core; + + /* GPIO SUS */ + struct { + const struct soc_gpio *mode; + const struct soc_gpio *direction; + const struct soc_gpio *level; + const struct soc_gpio *tpe; + const struct soc_gpio *tne; + const struct soc_gpio *ts; + const struct soc_gpio *we; + const struct soc_cfio *cfio_init; + const u32 cfio_entrynum; + }sus; + + +}; + +/* Configure GPIOs with mainboard provided settings */ +void setup_soc_gpios(const struct soc_gpio_map *gpio); + +/* Get GPIO pin value */ +int get_gpio(int gpio_num); +/* + * Get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of GPIO pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array); + +#endif |