diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-31 19:22:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:22:46 +0200 |
| commit | ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch) | |
| tree | 9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/intel/fsp_rangeley | |
| parent | 2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff) | |
| download | coreboot-ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1.tar.xz | |
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/gpio.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index e57d85541e..2a2061cb1a 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* CFIO Core Well Set 1 */ if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) { write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002); - for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { + for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0)) continue; write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0); @@ -78,7 +78,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* CFIO SUS Well Set 1 */ if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) { write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002); - for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { + for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0)) continue; write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0); diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 11aa60d60f..ab617506ef 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -137,7 +137,7 @@ static void write_pci_config_irqs(void) * the Interrupt Route registers in the ILB */ printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { if ((irq_dev->path.type != DEVICE_PATH_PCI) || (!irq_dev->enabled)) @@ -225,7 +225,7 @@ static void soc_pirq_init(device_t dev) write16(ir_base + i, ir->pcidev[i]); /* If the entry is more than just 0, print it out */ - if(ir->pcidev[i]) { + if (ir->pcidev[i]) { printk(BIOS_SPEW, " %d: ", i); for (j = 0; j < 4; j++) { pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; |