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authorMartin Roth <martin@coreboot.org>2019-10-23 21:46:03 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-10-30 11:16:56 +0000
commitff744bf0eee875a03dc98dd6792e3ed0ff4456a0 (patch)
tree691260ffe71abac0bb8e2a5607b0d6f1cfb16028 /src/southbridge/intel/fsp_rangeley
parent5331a7cff9ebf6f92542eee53e6556a4d5a0dc75 (diff)
downloadcoreboot-ff744bf0eee875a03dc98dd6792e3ed0ff4456a0.tar.xz
src/southbridge: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r--src/southbridge/intel/fsp_rangeley/early_smbus.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/gpio.h2
-rw-r--r--src/southbridge/intel/fsp_rangeley/soc.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/spi.c18
4 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c
index 48b7769925..da0c54be3f 100644
--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c
@@ -51,7 +51,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h
index 1a916f4dcc..6a27fea861 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.h
+++ b/src/southbridge/intel/fsp_rangeley/gpio.h
@@ -119,6 +119,6 @@ int get_gpio(int gpio_num);
* Get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of GPIO pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
#endif
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index ec66c430a9..3512f196d3 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -59,7 +59,7 @@ int soc_silicon_supported(int type, int rev)
}
/* Set bit in Function Disable register to hide this device */
-static void soc_hide_devfn(unsigned devfn)
+static void soc_hide_devfn(unsigned int devfn)
{
/* TODO Function Disable. */
}
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index d2f2a0bd32..f58677ba27 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -121,7 +121,7 @@ typedef struct ich_spi_controller {
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
- unsigned databytes;
+ unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
@@ -199,7 +199,7 @@ static u8 readb_(const void *addr)
{
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -207,7 +207,7 @@ static u16 readw_(const void *addr)
{
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -215,7 +215,7 @@ static u32 readl_(const void *addr)
{
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -223,21 +223,21 @@ static void writeb_(u8 b, const void *addr)
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
write32((unsigned long)addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@@ -397,13 +397,13 @@ typedef struct spi_transaction {
uint32_t offset;
} spi_transaction;
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;