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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-29 21:17:46 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-02 20:13:24 +0000
commit0b4298c24288f65a6b315864bf5b44ef54cfb30b (patch)
tree27c1871e2dab8b1e06874ab5c0448f1e04c47260 /src/southbridge/intel/fsp_rangeley
parent3d4923d85ab07f8ea2b30018763c6bef269e5796 (diff)
downloadcoreboot-0b4298c24288f65a6b315864bf5b44ef54cfb30b.tar.xz
intel/pci_devs: Regroup PCI xx_DEVID entries
Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r--src/southbridge/intel/fsp_rangeley/pci_devs.h39
1 files changed, 20 insertions, 19 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/pci_devs.h b/src/southbridge/intel/fsp_rangeley/pci_devs.h
index 29f9085a7b..89f3c5c230 100644
--- a/src/southbridge/intel/fsp_rangeley/pci_devs.h
+++ b/src/southbridge/intel/fsp_rangeley/pci_devs.h
@@ -26,87 +26,71 @@
/* Host Bridge */
#define SOC_DEV 0x0
#define SOC_FUNC 0
-# define SOC_DEVID 0x1f08
# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC)
/* PCIE Port 1 */
#define PCIE_PORT1_DEV 0x1
#define PCIE_PORT1_FUNC 0
-# define PCIE_PORT1_DEVID 0x1f10
# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC)
/* PCIE Port 2 */
#define PCIE_PORT2_DEV 0x2
#define PCIE_PORT2_FUNC 0
-# define PCIE_PORT2_DEVID 0x1f11
# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC)
/* PCIE Port 3 */
#define PCIE_PORT3_DEV 0x3
#define PCIE_PORT3_FUNC 0
-# define PCIE_PORT3_DEVID 0x1f12
# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC)
/* PCIE Port 4 */
#define PCIE_PORT4_DEV 0x4
#define PCIE_PORT4_FUNC 0
-# define PCIE_PORT4_DEVID 0x1f13
# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC)
/* Host Bridge, Fabric, and RAS Registers */
#define HOST_BRIDGE_DEV 0xe
#define HOST_BRIDGE_FUNC 0
-# define HOST_BRIDGE_DEVID 0x1f14
# define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC)
/* Root Complex Event Collector (RCEC) */
#define RCEC_DEV 0xf
#define RCEC_FUNC 0
-# define RCEC_DEVID 0x1f16
# define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC)
/* SMBus 2.0 1 */
#define SMBUS1_DEV 0x13
#define SMBUS1_FUNC 0
-# define SMBUS1_DEVID 0x1f15
# define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC)
/* Gigabit Ethernet (GbE) */
#define GBE_DEV 0x14
-#define GBE_DEVID 0x1f41
#define GBE1_DEV GBE_DEV
#define GBE1_FUNC 0
-# define GBE1_DEVID GBE_DEVID
# define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC)
#define GBE2_DEV GBE_DEV
#define GBE2_FUNC 1
-# define GBE2_DEVID GBE_DEVID
# define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC)
#define GBE3_DEV GBE_DEV
#define GBE3_FUNC 2
-# define GBE3_DEVID GBE_DEVID
# define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC)
#define GBE4_DEV GBE_DEV
#define GBE4_FUNC 3
-# define GBE4_DEVID GBE_DEVID
# define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC)
/* USB 2.0 */
#define USB2_DEV 0x16
#define USB2_FUNC 0
-# define USB2_DEVID 0x1f2c
# define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC)
/* SATA Gen 2 */
#define SATA2_DEV 0x17
#define SATA2_FUNC 0
-# define SATA2_DEVID 0x1f22
# define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC)
/* SATA Gen 3 */
#define SATA3_DEV 0x18
#define SATA3_FUNC 0
-# define SATA3_DEVID 0x1f32
# define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC)
/* Platform Control Unit (PCU) */
@@ -115,20 +99,37 @@
/* Low Pin Count (LPC/ISA) */
#define LPC_DEV PCU_DEV
#define LPC_FUNC 0
-# define LPC_DEVID 0x1f38
# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC)
# define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC)
/* SMBus 2.0 0 */
#define SMBUS0_DEV PCU_DEV
#define SMBUS0_FUNC 3
-# define SMBUS0_DEVID 0x1f3c
# define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC)
/* Intel QuickAssist Integrated Accelerator (IQIA) */
#define IQAT_DEV 0xb
#define IQAT_FUNC 0
-# define IQAT_DEVID 0x1f18
# define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC)
+#define SOC_DEVID 0x1f08
+#define PCIE_PORT1_DEVID 0x1f10
+#define PCIE_PORT2_DEVID 0x1f11
+#define PCIE_PORT3_DEVID 0x1f12
+#define PCIE_PORT4_DEVID 0x1f13
+#define HOST_BRIDGE_DEVID 0x1f14
+#define RCEC_DEVID 0x1f16
+#define SMBUS1_DEVID 0x1f15
+#define GBE_DEVID 0x1f41
+#define GBE1_DEVID GBE_DEVID
+#define GBE2_DEVID GBE_DEVID
+#define GBE3_DEVID GBE_DEVID
+#define GBE4_DEVID GBE_DEVID
+#define USB2_DEVID 0x1f2c
+#define SATA2_DEVID 0x1f22
+#define SATA3_DEVID 0x1f32
+#define LPC_DEVID 0x1f38
+#define SMBUS0_DEVID 0x1f3c
+#define IQAT_DEVID 0x1f18
+
#endif /* _RANGELEY_PCI_DEVS_H_ */