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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-03 08:01:05 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-04 15:57:39 +0000 |
| commit | 13f66507afdcde5170546e5ca1ce5a945895eb10 (patch) | |
| tree | 40c1d05a05b05b596f290c186aa59a8b4d9768ab /src/southbridge/intel/fsp_rangeley | |
| parent | 065857ee7fd61b05025d7a803e82f2b9b53cbc9a (diff) | |
| download | coreboot-13f66507afdcde5170546e5ca1ce5a945895eb10.tar.xz | |
device/mmio.h: Add include file for MMIO ops
MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/early_init.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/gpio.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/sata.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/spi.c | 2 |
6 files changed, 6 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 05e2812134..32e3bb5f4f 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -19,6 +19,7 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <pc80/mc146818rtc.h> diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index 740587a23c..831b1696c4 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include "soc.h" diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 4dee6362fb..b93bc09a62 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -23,6 +23,7 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 39d4362635..65001cfff1 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -19,6 +19,7 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index c4d6fdaf49..3f72a3dfe9 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#include <arch/io.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 34d0fa2111..99400fcbeb 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -19,7 +19,7 @@ #include <string.h> #include <commonlib/helpers.h> #include <delay.h> -#include <arch/io.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> |