summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/fsp_rangeley
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-08 11:16:06 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 05:46:59 +0000
commit7cdb047ce714378a644b7aa2c1f40a2e1a8d5750 (patch)
treeed3f8a336d9d8ac6caa48d3713dc4fa7d0d898c9 /src/southbridge/intel/fsp_rangeley
parent544878b56349a74e8cb7a0e9af899b5f7fc246fc (diff)
downloadcoreboot-7cdb047ce714378a644b7aa2c1f40a2e1a8d5750.tar.xz
cpu/x86/smm: Promote smm_memory_map()
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 2c2427eed1..f52a75205a 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -31,6 +31,7 @@
#include "southbridge/intel/fsp_rangeley/gpio.h"
#include "southbridge/intel/fsp_rangeley/romstage.h"
#include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
#include "gpio.h"
void main(FSP_INFO_HEADER *fsp_info_header)
@@ -121,9 +122,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e);
- post_code(0x4f);
+ if (CONFIG(SMM_TSEG))
+ smm_list_regions();
/* Load the ramstage. */
+ post_code(0x4f);
run_ramstage();
while (1);
}