diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-10-30 11:28:42 +0100 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2019-11-04 13:19:42 +0000 |
commit | 1644e4898535918dcd3f0225792b63a4441bda91 (patch) | |
tree | 2831f418d21bba1c109f73b8dec7c3514171b995 /src/southbridge/intel/fsp_rangeley | |
parent | 4ec67fc82cfcd6f9483e00215156a2296a44566e (diff) | |
download | coreboot-1644e4898535918dcd3f0225792b63a4441bda91.tar.xz |
sb/intel: Use defined CONFIG_HPET_ADDRESS
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/acpi/lpc.asl | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl index b53e98f6ce..a896dadc98 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl @@ -97,7 +97,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -120,15 +120,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } |