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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-25 10:12:14 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-13 09:28:39 +0000 |
| commit | 5709e03613b342f9dc00a659b6474c6ee510fcc3 (patch) | |
| tree | c4f5474ca13042126ca8e4d1fd00c4be405636e2 /src/southbridge/intel/fsp_rangeley | |
| parent | 59b4255c63b54739b9a095021508a13eab86c2a1 (diff) | |
| download | coreboot-5709e03613b342f9dc00a659b6474c6ee510fcc3.tar.xz | |
nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb.
* Set northbridge/southbridge and runtime detectable settings.
* Fill in values from devicetree.
This change is still a noop as the pei structure is completely overwritten
with the exsting mainboard pei structure.
The followup commit will migrate to devicetree.cb.
Tested on Lenovo T520, boots MRC path with the new devicetree settings.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
0 files changed, 0 insertions, 0 deletions