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| author | Joel Kitching <kitching@google.com> | 2018-08-17 15:15:02 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-22 15:32:30 +0000 |
| commit | 5846d5727a05e395d13317daba049e0e56e15d33 (patch) | |
| tree | 51f9e3027b8708891dabd9351bd45092de3f3581 /src/southbridge/intel/fsp_rangeley | |
| parent | 8f560d9b9c20c7e72b031e60cf0e828d7d27ec8e (diff) | |
| download | coreboot-5846d5727a05e395d13317daba049e0e56e15d33.tar.xz | |
acpi: remove CBMEM_ID_ACPI_GNVS_PTR entry
Since we can retrieve the address of ACPI GNVS directly
from CBMEM_ID_ACPI_GNVS, there is no need to store and
update a pointer separately.
TEST=Compile and run on Eve
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea
Reviewed-on: https://review.coreboot.org/28189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index a8b87574d3..88cc73fa82 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -434,7 +434,6 @@ static void southbridge_inject_dsdt(struct device *dev) if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); - acpi_save_gnvs((unsigned long)gnvs); #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); |