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authorMartin Roth <gaumless@gmail.com>2015-06-20 16:17:12 -0600
committerMartin Roth <gaumless@gmail.com>2015-06-23 22:48:45 +0200
commit59aa2b191b5b510e6a0567f6d2be5d1b97195c95 (patch)
tree2efb596e30a342423b7f18ff4984dcc0e207511b /src/southbridge/intel/fsp_rangeley
parent6ab0fd0a9455d35dde5c359845d35bb337b7666e (diff)
downloadcoreboot-59aa2b191b5b510e6a0567f6d2be5d1b97195c95.tar.xz
southbridge/intel: Create common IFD Kconfig and Makefile
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10613 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r--src/southbridge/intel/fsp_rangeley/Kconfig19
-rw-r--r--src/southbridge/intel/fsp_rangeley/Makefile.inc16
2 files changed, 6 insertions, 29 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig
index 71782be04a..2c8ceacd9a 100644
--- a/src/southbridge/intel/fsp_rangeley/Kconfig
+++ b/src/southbridge/intel/fsp_rangeley/Kconfig
@@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
+ select HAVE_INTEL_FIRMWARE
config EHCI_BAR
hex
@@ -52,21 +53,11 @@ config HPET_MIN_TICKS
hex
default 0x80
-if HAVE_FSP_BIN
-
-config INCLUDE_ME
- bool "Add Intel descriptor.bin file"
- default n
- help
- Include the descriptor.bin for rangeley.
-
-config ME_PATH
- string "Path to descriptor.bin file"
- depends on INCLUDE_ME
+config IFD_BIN_PATH
+ string
+ depends on HAVE_IFD_BIN
default "../intel/mainboard/intel/rangeley"
help
- The path of the descriptor.bin file.
-
-endif # HAVE_FSP_BIN
+ The path and filename to the descriptor.bin file.
endif
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc
index 0f9f59cdb5..1d35b54dc1 100644
--- a/src/southbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc
@@ -20,9 +20,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
+subdirs-y += ../common/firmware
ramstage-y += soc.c
ramstage-y += lpc.c
@@ -39,16 +37,4 @@ romstage-y += romstage.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
-
-ifeq ($(CONFIG_INCLUDE_ME),y)
-INTERMEDIATE+=rangeley_add_descriptor
-
-rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL)
- printf " DD Adding Intel Firmware Descriptor\n"
- dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \
- of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-endif
-
-PHONY += rangeley_add_descriptor
-
endif