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| author | Martin Roth <martinroth@google.com> | 2017-06-24 21:29:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-16 19:22:18 +0000 |
| commit | 7a1a3ad2ce3403f0379b72d30360e2bed02e9c26 (patch) | |
| tree | 0db32f6a8f2349b5ce269996f3246b13fec9d5af /src/southbridge/intel/fsp_rangeley | |
| parent | 9fa8ebe1a41fab33badfa4745708e1ad237e8a34 (diff) | |
| download | coreboot-7a1a3ad2ce3403f0379b72d30360e2bed02e9c26.tar.xz | |
southbridge/intel: add IS_ENABLED() around Kconfig symbol references
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/soc.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d621a41329..cbb2297c2c 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -94,7 +94,7 @@ static void soc_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) write8(ibase + ILB_SERIRQ_CNTL, 0); #endif } @@ -435,7 +435,7 @@ static void southbridge_inject_dsdt(device_t dev) memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); acpi_save_gnvs((unsigned long)gnvs); -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); #endif diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 0674dcae4f..4409f1e5f2 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -65,7 +65,7 @@ void soc_enable(device_t dev); #include <arch/acpi.h> void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void soc_log_state(void); #endif #else |