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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-11 20:52:30 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-16 09:50:03 +0000 |
| commit | ead574ed020063f1e6efe5289669ab67e2a76780 (patch) | |
| tree | dcda019fe464217fec69b12e834d9ec24b28f474 /src/southbridge/intel/fsp_rangeley | |
| parent | be11d9369b364253a29c8c4a7bc9a6288ff7df65 (diff) | |
| download | coreboot-ead574ed020063f1e6efe5289669ab67e2a76780.tar.xz | |
src: Get rid of duplicated includes
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/early_init.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/soc.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/spi.c | 1 |
4 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index ba4ebe061c..1ef8cb2add 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <version.h> -#include <device/pci_def.h> #include "pci_devs.h" #include "soc.h" diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 726fd3b9ef..3e7c17a74e 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -29,7 +29,6 @@ #include <elog.h> #include <string.h> #include <cbmem.h> -#include <arch/acpi.h> #include <arch/acpigen.h> #include "soc.h" #include "irq.h" diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 09172016e8..ffadee4bf2 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -62,7 +62,6 @@ int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); void soc_enable(struct device *dev); -#include <arch/acpi.h> void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); #if IS_ENABLED(CONFIG_ELOG) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 98ae708070..97548069ad 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -29,7 +29,6 @@ static int ich_status_poll(u16 bitmask, int wait_til_set); #ifdef __SMM__ -#include <arch/io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ |