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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-01 13:43:02 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-01 20:32:15 +0000 |
commit | f1b58b78351d7ed220673e688a2f7bc9e96da4e2 (patch) | |
tree | d8aae223f0e426f189cb4750b972a31e09d46b88 /src/southbridge/intel/fsp_rangeley | |
parent | 44e89af6e609874f2f18d30f1e66dce8b5a98eff (diff) | |
download | coreboot-f1b58b78351d7ed220673e688a2f7bc9e96da4e2.tar.xz |
device/pci: Fix PCI accessor headers
PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/acpi.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/early_init.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/early_smbus.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/early_usb.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/gpio.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/sata.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/soc.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/spi.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/watchdog.c | 1 |
11 files changed, 11 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index f88e99987f..e111881581 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -20,6 +20,7 @@ #include <arch/acpi.h> #include <southbridge/intel/fsp_rangeley/soc.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <version.h> #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 1ef8cb2add..05e2812134 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -19,6 +19,7 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <version.h> diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c index 9b47837dd1..48b7769925 100644 --- a/src/southbridge/intel/fsp_rangeley/early_smbus.c +++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> #include <southbridge/intel/common/smbus.h> diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c index 0bcd09d65d..896ef64bad 100644 --- a/src/southbridge/intel/fsp_rangeley/early_usb.c +++ b/src/southbridge/intel/fsp_rangeley/early_usb.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include "soc.h" diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index 0a287c4dc4..740587a23c 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> +#include <device/pci_ops.h> #include "soc.h" #include "gpio.h" diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 3e7c17a74e..4dee6362fb 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -23,6 +23,7 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> #include <arch/cpu.h> diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index ec60920ac5..39d4362635 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -19,6 +19,7 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> #include <cbmem.h> diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index c1d574941a..c4d6fdaf49 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -16,6 +16,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c index fd83342ac7..ec5cd073ed 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.c +++ b/src/southbridge/intel/fsp_rangeley/soc.c @@ -20,6 +20,7 @@ #include <delay.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include "soc.h" static int soc_revision_id = -1; diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 227422b270..34d0fa2111 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -20,6 +20,7 @@ #include <commonlib/helpers.h> #include <delay.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c index d7d3141e59..f18af8927c 100644 --- a/src/southbridge/intel/fsp_rangeley/watchdog.c +++ b/src/southbridge/intel/fsp_rangeley/watchdog.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <watchdog.h> |