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| author | Martin Roth <gaumless@gmail.com> | 2017-10-15 15:06:48 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:25:12 +0000 |
| commit | 264566c177dac98e67c2a4765fe08c5d8de10753 (patch) | |
| tree | 34cfe5ba3958d14dd976bd7f2a2fb58a3920c74d /src/southbridge/intel/i3100/chip.h | |
| parent | f6af8943e23b8ffa27df6ddb8e4a654387be0cb6 (diff) | |
| download | coreboot-264566c177dac98e67c2a4765fe08c5d8de10753.tar.xz | |
Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i3100/chip.h')
| -rw-r--r-- | src/southbridge/intel/i3100/chip.h | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h deleted file mode 100644 index 26a452a195..0000000000 --- a/src/southbridge/intel/i3100/chip.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -struct southbridge_intel_i3100_config -{ -#define I3100_GPIO_USE_MASK 0x03 -#define I3100_GPIO_USE_DEFAULT 0x00 -#define I3100_GPIO_USE_AS_NATIVE 0x01 -#define I3100_GPIO_USE_AS_GPIO 0x02 - -#define I3100_GPIO_SEL_MASK 0x0c -#define I3100_GPIO_SEL_DEFAULT 0x00 -#define I3100_GPIO_SEL_OUTPUT 0x04 -#define I3100_GPIO_SEL_INPUT 0x08 - -#define I3100_GPIO_LVL_MASK 0x30 -#define I3100_GPIO_LVL_DEFAULT 0x00 -#define I3100_GPIO_LVL_LOW 0x10 -#define I3100_GPIO_LVL_HIGH 0x20 -#define I3100_GPIO_LVL_BLINK 0x30 - -#define I3100_GPIO_INV_MASK 0xc0 -#define I3100_GPIO_INV_DEFAULT 0x00 -#define I3100_GPIO_INV_OFF 0x40 -#define I3100_GPIO_INV_ON 0x80 - - /* GPIO use select */ - u8 gpio[64]; - int sata_ports_implemented; - u32 pirq_a_d; - u32 pirq_e_h; -}; |