diff options
author | Martin Roth <gaumless@gmail.com> | 2017-10-15 15:06:48 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:25:12 +0000 |
commit | 264566c177dac98e67c2a4765fe08c5d8de10753 (patch) | |
tree | 34cfe5ba3958d14dd976bd7f2a2fb58a3920c74d /src/southbridge/intel/i3100/i3100.c | |
parent | f6af8943e23b8ffa27df6ddb8e4a654387be0cb6 (diff) | |
download | coreboot-264566c177dac98e67c2a4765fe08c5d8de10753.tar.xz |
Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i3100/i3100.c')
-rw-r--r-- | src/southbridge/intel/i3100/i3100.c | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/src/southbridge/intel/i3100/i3100.c b/src/southbridge/intel/i3100/i3100.c deleted file mode 100644 index 7becc0e4e5..0000000000 --- a/src/southbridge/intel/i3100/i3100.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include "i3100.h" - -void i3100_enable(device_t dev) -{ - device_t lpc_dev; - u8 func; - volatile u32 *disable; - - if (dev->enabled) - return; - - /* - * To disable an integrated southbridge device, set the corresponding - * flag in the Function Disable register. - */ - - /* Temporarily enable the root complex register block at 0xa0000000. */ - lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0)); - pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0)); - disable = (volatile u32 *) 0xa0003418; - func = PCI_FUNC(dev->path.pci.devfn); - switch (PCI_SLOT(dev->path.pci.devfn)) { - case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */ - *disable |= (1 << (func == 0x0 ? 14 : func)); - break; - case 0x1d: /* UHCI (fn0, fn1), EHCI (fn7) */ - *disable |= (1 << (func + 8)); - break; - case 0x1c: /* PCIe ports B0-B3 (fn0-fn3) */ - *disable |= (1 << (func + 16)); - break; - } - /* Disable the root complex register block. */ - pci_write_config32(lpc_dev, 0xf0, 0); -} - -struct chip_operations southbridge_intel_i3100_ops = { - CHIP_NAME("Intel 3100 Southbridge") -}; |