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authorStefan Reinauer <stepan@coresystems.de>2010-02-22 06:09:43 +0000
committerStefan Reinauer <stepan@openbios.org>2010-02-22 06:09:43 +0000
commitde3206a7bebce99f11e753164cc4d46357bba96a (patch)
tree9843d883940e372dd357b1357ecd7eaba3e3365f /src/southbridge/intel/i3100
parentd650e9934ff8da9b9cb69e42e642c0ee6d390bf6 (diff)
downloadcoreboot-de3206a7bebce99f11e753164cc4d46357bba96a.tar.xz
This is a general cleanup patch
- drop include/part and move files to include/ - get rid lots of warnings - make resource allocator happy with w83627thg - trivial cbmem resume fix - fix payload and log level settings in abuild - fix kontron mptable for virtual wire mode - drop some dead includes and dead code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i3100')
-rw-r--r--src/southbridge/intel/i3100/i3100_pciexp_portb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i3100/i3100_pciexp_portb.c b/src/southbridge/intel/i3100/i3100_pciexp_portb.c
index 7fd17188e7..0777a11eb1 100644
--- a/src/southbridge/intel/i3100/i3100_pciexp_portb.c
+++ b/src/southbridge/intel/i3100/i3100_pciexp_portb.c
@@ -28,7 +28,7 @@
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
#define PCIE_LCTL 0x50
#define PCIE_LSTS 0x52