diff options
| author | Ed Swierk <eswierk@arastra.com> | 2008-04-01 02:36:59 +0000 |
|---|---|---|
| committer | Ed Swierk <eswierk@arastra.com> | 2008-04-01 02:36:59 +0000 |
| commit | c4e052cd5089019dc67b4fa176bca6d8d19de30d (patch) | |
| tree | 86802951111145e526401af3029372e6ef51fc05 /src/southbridge/intel/i3100 | |
| parent | 2c6b33ce3e2eb287e6a0b25d46b96ba7876fe17a (diff) | |
| download | coreboot-c4e052cd5089019dc67b4fa176bca6d8d19de30d.tar.xz | |
The early init code of several Intel southbridge chipsets calls
pci_locate_device() to locate the SMBus controller and LPC bridge
devices on the PCI bus. Since these devices are always located at a
fixed PCI bus:device:function, the code can be simplified by
hardcoding the devices.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i3100')
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_early_lpc.c | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_early_smbus.c | 8 |
2 files changed, 4 insertions, 18 deletions
diff --git a/src/southbridge/intel/i3100/i3100_early_lpc.c b/src/southbridge/intel/i3100/i3100_early_lpc.c index fbefcd6acb..742cffa2ca 100644 --- a/src/southbridge/intel/i3100/i3100_early_lpc.c +++ b/src/southbridge/intel/i3100/i3100_early_lpc.c @@ -20,12 +20,7 @@ static void i3100_enable_superio(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_3100_LPC), 0); - if (dev == PCI_DEV_INVALID) { - die("LPC bridge not found\r\n"); - } + device_t dev = PCI_DEV(0x0, 0x1f, 0x0); /* Enable decoding of I/O locations for SuperIO devices */ pci_write_config16(dev, 0x82, 0x340f); @@ -33,12 +28,7 @@ static void i3100_enable_superio(void) static void i3100_halt_tco_timer(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_3100_LPC), 0); - if (dev == PCI_DEV_INVALID) { - die("LPC bridge not found\r\n"); - } + device_t dev = PCI_DEV(0, 0x1f, 0); /* Temporarily enable the ACPI I/O range at 0x4000 */ pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); diff --git a/src/southbridge/intel/i3100/i3100_early_smbus.c b/src/southbridge/intel/i3100/i3100_early_smbus.c index 3e31864c22..b7edb9b68c 100644 --- a/src/southbridge/intel/i3100/i3100_early_smbus.c +++ b/src/southbridge/intel/i3100/i3100_early_smbus.c @@ -24,12 +24,8 @@ static void enable_smbus(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_3100_SMB), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBus controller not found\r\n"); - } + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + print_spew("SMBus controller enabled\r\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); |