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authorThomas Jourdan <thomas.jourdan@gmail.com>2009-07-01 17:01:17 +0000
committerMyles Watson <mylesgw@gmail.com>2009-07-01 17:01:17 +0000
commit1a692d817650068e2125036d25bbaf2f3e9ec876 (patch)
tree76d51c38f3f85a0a121a7f7bfa82db1deab3ed96 /src/southbridge/intel/i3100
parent6c96517a132ce26f906c8e38e19ebaab8b736e9a (diff)
downloadcoreboot-1a692d817650068e2125036d25bbaf2f3e9ec876.tar.xz
Add support for the Intel Eagle Heights development board.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i3100')
-rw-r--r--src/southbridge/intel/i3100/Config.lb1
-rw-r--r--src/southbridge/intel/i3100/cmos_failover.c35
-rw-r--r--src/southbridge/intel/i3100/i3100_lpc.c90
-rw-r--r--src/southbridge/intel/i3100/i3100_pciexp_portb.c94
-rw-r--r--src/southbridge/intel/i3100/i3100_sata.c88
5 files changed, 270 insertions, 38 deletions
diff --git a/src/southbridge/intel/i3100/Config.lb b/src/southbridge/intel/i3100/Config.lb
index 7b6b4aed31..f67a06a736 100644
--- a/src/southbridge/intel/i3100/Config.lb
+++ b/src/southbridge/intel/i3100/Config.lb
@@ -26,3 +26,4 @@ driver i3100_ehci.o
driver i3100_smbus.o
driver i3100_pci.o
object i3100_reset.o
+object i3100_pciexp_portb.o
diff --git a/src/southbridge/intel/i3100/cmos_failover.c b/src/southbridge/intel/i3100/cmos_failover.c
new file mode 100644
index 0000000000..4a134dd609
--- /dev/null
+++ b/src/southbridge/intel/i3100/cmos_failover.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "i3100.h"
+
+#define RTC_FAILED (1 <<2)
+#define GEN_PMCON_3 0xa4
+
+static void check_cmos_failed(void)
+{
+ u8 byte;
+ byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ if (byte & RTC_FAILED) {
+ // clear bit 1 and bit 2
+ byte = cmos_read(RTC_BOOT_BYTE);
+ byte &= 0x0c;
+ byte |= CONFIG_MAX_REBOOT_CNT << 4;
+ cmos_write(byte, RTC_BOOT_BYTE);
+ }
+}
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c
index 8e0c460880..f8584cadb0 100644
--- a/src/southbridge/intel/i3100/i3100_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_lpc.c
@@ -35,12 +35,18 @@
#define GPIO_BAR 0x48
#define RCBA 0xf0
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xA0
+#define GEN_PMCON_2 0xA2
+#define GEN_PMCON_3 0xA4
+
#define NMI_OFF 0
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
#define ALL (0xff << 24)
@@ -93,11 +99,10 @@ static void setup_ioapic(device_t dev)
}
/* Put the APIC in virtual wire mode */
- l[0] = 0x10;
+ l[0] = 0x12;
l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
}
-#define SERIRQ_CNTL 0x64
static void i3100_enable_serial_irqs(device_t dev)
{
/* set packet length and toggle silent mode bit */
@@ -257,6 +262,68 @@ static void i3100_pirq_init(device_t dev)
}
}
+static void i3100_power_options(device_t dev) {
+ u8 reg8;
+ u16 reg16;
+ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int nmi_option;
+
+ /* Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ */
+ get_option(&pwr_on, "power_on_after_fail");
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ reg8 &= 0xfe;
+ if (pwr_on) {
+ reg8 &= ~1;
+ } else {
+ reg8 |= 1;
+ }
+ /* avoid #S4 assertions */
+ reg8 |= (3 << 4);
+ /* minimum asssertion is 1 to 2 RTCCLK */
+ reg8 &= ~(1 << 3);
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
+
+ /* Set up NMI on errors. */
+ reg8 = inb(0x61);
+ /* Higher Nibble must be 0 */
+ reg8 &= 0x0f;
+ /* IOCHK# NMI Enable */
+ reg8 &= ~(1 << 3);
+ /* PCI SERR# Enable */
+ // reg8 &= ~(1 << 2);
+ /* PCI SERR# Disable for now */
+ reg8 |= (1 << 2);
+ outb(reg8, 0x61);
+
+ reg8 = inb(0x70);
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ /* Set NMI. */
+ printk_info ("NMI sources enabled.\n");
+ reg8 &= ~(1 << 7);
+ } else {
+ /* Can't mask NMI from PCI-E and NMI_NOW */
+ printk_info ("NMI sources disabled.\n");
+ reg8 |= ( 1 << 7);
+ }
+ outb(reg8, 0x70);
+
+ // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 &= ~((3 << 0) | (1 << 10));
+ reg16 |= (1 << 3) | (1 << 5);
+ /* CLKRUN_EN */
+ // reg16 |= (1 << 2);
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ // Set the board's GPI routing.
+ // i82801gx_gpi_routing(dev);
+}
static void i3100_gpio_init(device_t dev)
{
@@ -296,9 +363,6 @@ static void i3100_gpio_init(device_t dev)
static void lpc_init(struct device *dev)
{
- u8 byte;
- int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
-
setup_ioapic(dev);
/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
@@ -306,18 +370,12 @@ static void lpc_init(struct device *dev)
i3100_enable_serial_irqs(dev);
- get_option(&pwr_on, "power_on_after_fail");
- byte = pci_read_config8(dev, 0xa4);
- byte &= 0xfe;
- if (!pwr_on) {
- byte |= 1;
- }
- pci_write_config8(dev, 0xa4, byte);
- printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
-
/* Set up the PIRQ */
i3100_pirq_init(dev);
+ /* Setup power options */
+ i3100_power_options(dev);
+
/* Set the state of the gpio lines */
i3100_gpio_init(dev);
diff --git a/src/southbridge/intel/i3100/i3100_pciexp_portb.c b/src/southbridge/intel/i3100/i3100_pciexp_portb.c
new file mode 100644
index 0000000000..7fd17188e7
--- /dev/null
+++ b/src/southbridge/intel/i3100/i3100_pciexp_portb.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pciexp.h>
+#include <arch/io.h>
+#include "chip.h"
+#include <part/hard_reset.h>
+
+#define PCIE_LCTL 0x50
+#define PCIE_LSTS 0x52
+
+typedef struct northbridge_intel_i3100_config config_t;
+
+static void pcie_init(struct device *dev)
+{
+}
+
+static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
+{
+ u16 val;
+ u16 ctl;
+ int flag = 0;
+ do {
+ val = pci_read_config16(dev, PCIE_LSTS);
+ printk_debug("pcie portb link status: %02x\n", val);
+ if ((val & (1<<10)) && (!flag)) { /* training error */
+ ctl = pci_read_config16(dev, PCIE_LCTL);
+ pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
+ val = pci_read_config16(dev, PCIE_LSTS);
+ printk_debug("pcie portb reset link status: %02x\n", val);
+ flag=1;
+ hard_reset();
+ }
+ } while (val & (3<<10));
+ return pciexp_scan_bridge(dev, max);
+}
+
+static struct device_operations pcie_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pcie_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = 0,
+};
+
+static struct pci_driver pci_driver_0 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0,
+};
+
+static struct pci_driver pci_driver_1 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1,
+};
+
+static struct pci_driver pci_driver_2 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2,
+};
+
+static struct pci_driver pci_driver_3 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3,
+};
diff --git a/src/southbridge/intel/i3100/i3100_sata.c b/src/southbridge/intel/i3100/i3100_sata.c
index c3e3ed165d..d300ba4e15 100644
--- a/src/southbridge/intel/i3100/i3100_sata.c
+++ b/src/southbridge/intel/i3100/i3100_sata.c
@@ -27,32 +27,76 @@
#include <device/pci_ops.h>
#include "i3100.h"
+#define SATA_CMD 0x04
+#define SATA_PI 0x09
+#define SATA_PTIM 0x40
+#define SATA_STIM 0x42
+#define SATA_D1TIM 0x44
+#define SATA_SYNCC 0x48
+#define SATA_SYNCTIM 0x4A
+#define SATA_IIOC 0x54
+#define SATA_MAP 0x90
+#define SATA_PCS 0x91
+#define SATA_ACR0 0xA8
+#define SATA_ACR1 0xAC
+#define SATA_ATC 0xC0
+#define SATA_ATS 0xC4
+#define SATA_SP 0xD0
+
+typedef struct southbridge_intel_i3100_config config_t;
+
static void sata_init(struct device *dev)
{
- /* Enable SATA devices */
-
- printk_debug("SATA init\n");
- /* SATA configuration */
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x09, 0x8f);
-
- /* Set timings */
- pci_write_config16(dev, 0x40, 0x0a307);
- pci_write_config16(dev, 0x42, 0x0a307);
+ u8 ahci;
- /* Sync DMA */
- pci_write_config16(dev, 0x48, 0x000f);
- pci_write_config16(dev, 0x4a, 0x1111);
-
- /* Fast ATA */
- pci_write_config16(dev, 0x54, 0x1000);
-
- /* Select IDE mode */
- pci_write_config8(dev, 0x90, 0x00);
-
- /* Enable ports 0-3 */
- pci_write_config8(dev, 0x92, 0x0f);
+ /* Get the chip configuration */
+ ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
+ /* Enable SATA devices */
+ printk_info("SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
+
+ if(ahci) {
+ /* AHCI mode */
+ pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
+
+ /* Enable ports */
+ pci_write_config8(dev, SATA_PCS, 0x03);
+ pci_write_config8(dev, SATA_PCS + 1, 0x0F);
+
+ /* Setup timings */
+ pci_write_config16(dev, SATA_PTIM, 0x8000);
+ pci_write_config16(dev, SATA_STIM, 0x8000);
+
+ /* Synchronous DMA */
+ pci_write_config8(dev, SATA_SYNCC, 0);
+ pci_write_config16(dev, SATA_SYNCTIM, 0);
+
+ /* IDE I/O configuration */
+ pci_write_config32(dev, SATA_IIOC, 0);
+
+ } else {
+ /* SATA configuration */
+ pci_write_config8(dev, SATA_CMD, 0x07);
+ pci_write_config8(dev, SATA_PI, 0x8f);
+
+ /* Set timings */
+ pci_write_config16(dev, SATA_PTIM, 0x0a307);
+ pci_write_config16(dev, SATA_STIM, 0x0a307);
+
+ /* Sync DMA */
+ pci_write_config8(dev, SATA_SYNCC, 0x0f);
+ pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
+
+ /* Fast ATA */
+ pci_write_config16(dev, SATA_IIOC, 0x1000);
+
+ /* Select IDE mode */
+ pci_write_config8(dev, SATA_MAP, 0x00);
+
+ /* Enable ports 0-3 */
+ pci_write_config8(dev, SATA_PCS + 1, 0x0f);
+
+ }
printk_debug("SATA Enabled\n");
}