diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-22 11:42:32 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-22 11:42:32 +0000 |
| commit | c02b4fc9db3c3c1e263027382697b566127f66bb (patch) | |
| tree | 11bd18488e360e5c1beeb9ccb852ef4489c3689a /src/southbridge/intel/i3100 | |
| parent | 27852aba6787617ca5656995cbc7e8ef0a3ea22c (diff) | |
| download | coreboot-c02b4fc9db3c3c1e263027382697b566127f66bb.tar.xz | |
printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i3100')
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_pciexp_portb.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_sata.c | 4 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c index 2d3b1fbf6f..4612c916d2 100644 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ b/src/southbridge/intel/i3100/i3100_lpc.c @@ -232,7 +232,7 @@ static void i3100_power_options(device_t dev) { /* minimum asssertion is 1 to 2 RTCCLK */ reg8 &= ~(1 << 3); pci_write_config8(dev, GEN_PMCON_3, reg8); - printk_info("set power %s after power fail\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -251,11 +251,11 @@ static void i3100_power_options(device_t dev) { get_option(&nmi_option, "nmi"); if (nmi_option) { /* Set NMI. */ - printk_info ("NMI sources enabled.\n"); + printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); } else { /* Can't mask NMI from PCI-E and NMI_NOW */ - printk_info ("NMI sources disabled.\n"); + printk(BIOS_INFO, "NMI sources disabled.\n"); reg8 |= ( 1 << 7); } outb(reg8, 0x70); diff --git a/src/southbridge/intel/i3100/i3100_pciexp_portb.c b/src/southbridge/intel/i3100/i3100_pciexp_portb.c index a987da02f5..31502a46de 100644 --- a/src/southbridge/intel/i3100/i3100_pciexp_portb.c +++ b/src/southbridge/intel/i3100/i3100_pciexp_portb.c @@ -46,12 +46,12 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) int flag = 0; do { val = pci_read_config16(dev, PCIE_LSTS); - printk_debug("pcie portb link status: %02x\n", val); + printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val); if ((val & (1<<10)) && (!flag)) { /* training error */ ctl = pci_read_config16(dev, PCIE_LCTL); pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5))); val = pci_read_config16(dev, PCIE_LSTS); - printk_debug("pcie portb reset link status: %02x\n", val); + printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val); flag=1; hard_reset(); } diff --git a/src/southbridge/intel/i3100/i3100_sata.c b/src/southbridge/intel/i3100/i3100_sata.c index a124d10d11..cafb68fe0d 100644 --- a/src/southbridge/intel/i3100/i3100_sata.c +++ b/src/southbridge/intel/i3100/i3100_sata.c @@ -53,7 +53,7 @@ static void sata_init(struct device *dev) ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03; /* Enable SATA devices */ - printk_info("SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); + printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); if(ahci) { /* AHCI mode */ @@ -97,7 +97,7 @@ static void sata_init(struct device *dev) pci_write_config8(dev, SATA_PCS + 1, 0x0f); } - printk_debug("SATA Enabled\n"); + printk(BIOS_DEBUG, "SATA Enabled\n"); } static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) |