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| author | Keith Short <keithshort@chromium.org> | 2019-01-15 10:32:22 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-17 13:02:08 +0000 |
| commit | d1215269a7bc9b3df82548a7ebdb0e468b18e1df (patch) | |
| tree | a31d623f7f8b2a06d1f66bfb8fb11f1e081478b0 /src/southbridge/intel/i82371eb/Kconfig | |
| parent | e371d421137901043ba495f8e4f5063be26b6764 (diff) | |
| download | coreboot-d1215269a7bc9b3df82548a7ebdb0e468b18e1df.tar.xz | |
src/mainboard/google/sarien: query recovery mode from Cr50
On the Sarien/Arcada platforms, the EC is not trusted to provide
the state of the ESC+REFRESH+PWR recovery combination. On these
platforms the Cr50 latches the state of REFRESH+PWR for use as the
recovery mode key combination.
BUG=b:122715254
BRANCH=none
TEST=Verify recovery mode screen shown after pressing REFRESH+PWR
Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82371eb/Kconfig')
0 files changed, 0 insertions, 0 deletions