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authorUwe Hermann <uwe@hermann-uwe.de>2007-05-03 08:50:37 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2007-05-03 08:50:37 +0000
commitd436a4b4bc035a3756a57ae8e632e16f7a95b9c9 (patch)
treee61a55cb4f885f08b52cf04a37c8d7232cdc0ead /src/southbridge/intel/i82371eb/i82371eb.c
parent941a6f078ece125a5c116315c82fcd3cb1feaf42 (diff)
downloadcoreboot-d436a4b4bc035a3756a57ae8e632e16f7a95b9c9.tar.xz
Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,
as that is not RAM but used for other stuff. First try at PCI init added to src/mainboard/tyan/s1846/Config.lb. Use a real payload (FILO) per default now. Note: this cannot boot a payload, yet, but it gets a lot further now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82371eb/i82371eb.c')
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c
new file mode 100644
index 0000000000..2073a82eee
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "i82371eb.h"
+
+void i82371eb_enable(device_t dev)
+{
+ /* TODO. */
+}
+
+struct chip_operations southbridge_intel_i82371eb_ops = {
+ CHIP_NAME("Intel 82371EB Southbridge")
+ .enable_dev = i82371eb_enable,
+};