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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-01 15:56:27 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-02 15:32:46 +0000 |
commit | 320d6e88afa56f2c11d9118faf6e47036fcc6540 (patch) | |
tree | 79aaf313928a3493edc89898ef6dc59b699ccf84 /src/southbridge/intel/i82371eb/i82371eb.h | |
parent | bd3dd59f4ae9765e7ced9eb402785db2872ef33a (diff) | |
download | coreboot-320d6e88afa56f2c11d9118faf6e47036fcc6540.tar.xz |
intel/i82371eb: Drop unused code
Change-Id: I71b5e46efac718df6d4b52d27a20fe1cf6d96427
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82371eb/i82371eb.h')
-rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index d35b215ab1..55242effca 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,11 +19,6 @@ #if !defined(__ACPI__) -#include <device/device.h> -void i82371eb_enable(struct device *dev); - -void i82371eb_hard_reset(void); - void enable_smbus(void); void enable_pm(void); @@ -45,7 +40,6 @@ int smbus_read_byte(u8 device, u8 address); #define XBCS 0x4e /* X-Bus chip select register */ #define GENCFG 0xb0 /* General configuration register */ -#define RC 0xcf9 /* Reset control register */ /* IDE */ #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ @@ -115,8 +109,6 @@ int smbus_read_byte(u8 device, u8 address); #define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */ #define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */ #define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */ -#define SRST (1 << 1) /* System Reset */ -#define RCPU (1 << 2) /* Reset CPU */ #define SMB_HST_EN (1 << 0) /* Host Interface Enable */ #define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ #define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */ |