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author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-11-30 02:08:26 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-11-30 02:08:26 +0000 |
commit | 9da69f83d9fd3b872afb38c24b373b0807c76b00 (patch) | |
tree | 10f1597c46c6dcfcf125953421c61fe8c5aebf64 /src/southbridge/intel/i82371eb/i82371eb.h | |
parent | 8d43b343cf390f67461b3121d101d16ebf9b5975 (diff) | |
download | coreboot-9da69f83d9fd3b872afb38c24b373b0807c76b00.tar.xz |
Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):
- Implement ISA related support:
- Initialize the RTC
- Enable access to all BIOS regions (but _not_ write access to ROM)
- Enable ISA (not EIO) support
- Without the *_isa.c file, the Super I/O init is never performed
- Improve IDE support:
- Add config option to enable Ultra DMA/33 for each disk
- Add config option to enable legacy IDE port access
- Implement hard reset support
- Implement USB controller support
- Various code cleanups and improvements
The code partially supports southbridges other than the 82371EB (but
which are very similar), more complete support will follow.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82371eb/i82371eb.h')
-rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 51 |
1 files changed, 41 insertions, 10 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 0693d4d564..7b8cce0e38 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -18,27 +18,58 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SOUTHBRIDGE_INTEL_I82371EB_H -#define SOUTHBRIDGE_INTEL_I82371EB_H +#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H +#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #ifndef __ROMCC__ #include "chip.h" void i82371eb_enable(device_t dev); #endif -#define XBCS 0x4e /* X-Bus Chip Select register */ +/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the + * 'reg' variable, otherwise it clears those bits. + * + * Examples: + * reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5)); + * reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR)); + */ +/* TODO: Move into some global header file? */ +#define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits))) -/* SMBus */ -#define SMBBA 0x90 /* SMBus Base Address */ -#define SMBHSTCFG 0xd2 /* SMBus Host Configuration */ +#define XBCS 0x4e /* X-Bus chip select register */ +#define GENCFG 0xb0 /* General configuration register */ +#define RC 0xcf9 /* Reset control register */ /* IDE */ #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ #define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */ +#define UDMACTL 0x48 /* Ultra DMA/33 control register */ +#define UDMATIM 0x4a /* Ultra DMA/33 timing register */ + +/* SMBus */ +#define SMBBA 0x90 /* SMBus base address */ +#define SMBHSTCFG 0xd2 /* SMBus host configuration */ + +/* Power management (ACPI) */ +#define PMBA 0x40 /* Power management base address */ +#define PMREGMISC 0x80 /* Miscellaneous power management */ /* Bit definitions */ -#define IOSE (1 << 0) /* I/O Space Enable */ -#define SMB_HST_EN (1 << 0) /* Host Interface Enable */ -#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ +#define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ +#define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */ +#define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */ +#define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */ +#define SRST (1 << 1) /* System Reset */ +#define RCPU (1 << 2) /* Reset CPU */ +#define SMB_HST_EN (1 << 0) /* Host Interface Enable */ +#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ +#define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */ +#define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */ +#define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */ +#define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */ +#define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ +#define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ +#define ISA (1 << 0) /* Select ISA */ +#define EIO (0 << 0) /* Select EIO */ -#endif /* SOUTHBRIDGE_INTEL_I82371EB_H */ +#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ |