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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-29 10:37:52 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-29 10:37:52 +0000 |
| commit | 1410c2d2192c4f2e782ac9af97c9df0165c3974e (patch) | |
| tree | 480da58f1adfd2c4e7e9632cfe19049ef0ce2105 /src/southbridge/intel/i82371eb/i82371eb.h | |
| parent | 861f96403777c8f4475ca94613c5142075dd0cdf (diff) | |
| download | coreboot-1410c2d2192c4f2e782ac9af97c9df0165c3974e.tar.xz | |
Intel 82371EB: Add IDE init support.
In a mainboard's Config.lb file you can configure whether the primary
and/or secondary IDE interfaces shall be enabled.
Also, various fixups in the rest of the southbridge code, most notably
the early SMBus code, plus some documentation improvements.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey_osgood@verizon.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82371eb/i82371eb.h')
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 6db363b857..096f8722df 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -18,17 +18,28 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef I82371EB_H -#define I82371EB_H +#ifndef SOUTHBRIDGE_INTEL_I82371EB_H +#define SOUTHBRIDGE_INTEL_I82371EB_H #ifndef __ROMCC__ - #include "chip.h" +void i82371eb_enable(device_t dev); +#endif +#define PCICMD 0x04 /* PCI Command Register */ #define XBCS 0x4e /* X-Bus Chip Select register */ -void i82371eb_enable(device_t dev); +/* SMBus */ +#define SMBBA 0x90 /* SMBus Base Address */ +#define SMBHSTCFG 0xd2 /* SMBus Host Configuration */ -#endif +/* IDE */ +#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ +#define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */ + +/* Bit definitions */ +#define IOSE (1 << 0) /* I/O Space Enable */ +#define SMB_HST_EN (1 << 0) /* Host Interface Enable */ +#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ -#endif /* I82371EB_H */ +#endif /* SOUTHBRIDGE_INTEL_I82371EB_H */ |