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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-27 21:43:58 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-27 21:43:58 +0000 |
| commit | 4cb85533dd14731048b65d8f2e165a271b98953e (patch) | |
| tree | 800469af7557955e815df69ab36efa8156f81b49 /src/southbridge/intel/i82371eb/i82371eb.h | |
| parent | 4834a4f2063509cbdb2ab20114f18664d5e9caf2 (diff) | |
| download | coreboot-4cb85533dd14731048b65d8f2e165a271b98953e.tar.xz | |
Init for the Intel 82371EB southbridge: make all ROM/BIOS regions
accessible (but not writable), so that reading/loading a payload
from that area can work (for instance).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82371eb/i82371eb.h')
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 275eee6937..6db363b857 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -25,6 +25,8 @@ #include "chip.h" +#define XBCS 0x4e /* X-Bus Chip Select register */ + void i82371eb_enable(device_t dev); #endif |