diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/intel/i82371eb/isa.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82371eb/isa.c')
| -rw-r--r-- | src/southbridge/intel/i82371eb/isa.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index b4041ef9e0..00b3866665 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -23,13 +23,13 @@ #include <pc80/isa-dma.h> #include <pc80/mc146818rtc.h> #include <arch/ioapic.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #include <arch/acpi.h> #include <arch/acpigen.h> #endif #include "i82371eb.h" -#if IS_ENABLED(CONFIG_IOAPIC) +#if CONFIG(IOAPIC) static void enable_intel_82093aa_ioapic(void) { u16 reg16; @@ -85,7 +85,7 @@ static void isa_init(struct device *dev) /* Initialize ISA DMA. */ isa_dma_init(); -#if IS_ENABLED(CONFIG_IOAPIC) +#if CONFIG(IOAPIC) /* * Unlike most other southbridges the 82371EB doesn't have a built-in * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs @@ -116,7 +116,7 @@ static void sb_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -#if IS_ENABLED(CONFIG_IOAPIC) +#if CONFIG(IOAPIC) res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; @@ -125,7 +125,7 @@ static void sb_read_resources(struct device *dev) #endif } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void southbridge_acpi_fill_ssdt_generator(struct device *device) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); @@ -137,7 +137,7 @@ static const struct device_operations isa_ops = { .read_resources = sb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif |