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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-18 16:33:39 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-21 07:00:45 +0000
commit12b121cdb450d96309dd96b2ccc25fc5501d2250 (patch)
tree1d94c123c23512b811d69d9876ac9a860bbbe0f6 /src/southbridge/intel/i82371eb
parent544b572c07bb09aba36705b5d8ffca3b793323f6 (diff)
downloadcoreboot-12b121cdb450d96309dd96b2ccc25fc5501d2250.tar.xz
southbridge/intel: Tidy up preprocessor and headers
Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82371eb')
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.h16
-rw-r--r--src/southbridge/intel/i82371eb/ide.c1
-rw-r--r--src/southbridge/intel/i82371eb/smbus.c1
3 files changed, 12 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 5e0ff3f418..77931cb20c 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -17,18 +17,22 @@
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
-#if !defined(__PRE_RAM__)
-#include <device/device.h>
-#include "chip.h"
+#if !defined(__ACPI__)
+#ifndef __ROMCC__
+#include <device/device.h>
void i82371eb_enable(struct device *dev);
+#endif
+
void i82371eb_hard_reset(void);
-#else
+
void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
void enable_pm(void);
+
+#if ENV_ROMSTAGE
+int smbus_read_byte(u8 device, u8 address);
#endif
+
#endif
/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c
index 33f7ac7569..7a72a6552d 100644
--- a/src/southbridge/intel/i82371eb/ide.c
+++ b/src/southbridge/intel/i82371eb/ide.c
@@ -22,6 +22,7 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
+#include "chip.h"
#include "i82371eb.h"
/**
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index afc4d6ac1e..36a9f560fc 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <device/smbus.h>
#include <southbridge/intel/common/smbus.h>
+#include "chip.h"
#include "i82371eb.h"
static void pwrmgt_enable(struct device *dev)