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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 12:05:38 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-25 09:18:22 +0000 |
| commit | 1fa240a3c5d2a6e8cd63eff24f227abc3333753b (patch) | |
| tree | 19b26ef5f947bc4d82461b20ec263d4feabbc1c9 /src/southbridge/intel/i82371eb | |
| parent | df0c731e688f55caf61fa721d32f1725e241aca5 (diff) | |
| download | coreboot-1fa240a3c5d2a6e8cd63eff24f227abc3333753b.tar.xz | |
cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK
Console is not yet enabled in bootblock. This will be done in
a different CL.
Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82371eb')
| -rw-r--r-- | src/southbridge/intel/i82371eb/Kconfig | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/bootblock.c | 9 |
3 files changed, 10 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index f5b5f4ee1e..d0eec0e5f4 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -4,8 +4,3 @@ config SOUTHBRIDGE_INTEL_I82371EB select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET bool - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82371eb/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 131010fc3d..390fd9783e 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -16,6 +16,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) +bootblock-y += bootblock.c + ramstage-y += i82371eb.c ramstage-y += isa.c ramstage-y += ide.c diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 2b8cd1f4b7..a6d62e03e0 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <device/pci_type.h> +#include <cpu/intel/car/bootblock.h> #include "i82371eb.h" #define PCI_ID(VENDOR_ID, DEVICE_ID) \ @@ -34,7 +35,13 @@ static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) return PCI_DEV_INVALID; } -static void bootblock_southbridge_init(void) +/* TODO: Does not need to happen before console init. */ +/* The whole rom is not accessible before this so limit + the bootblock size. */ +#if CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000 +#error "CONFIG_C_ENV_BOOTBLOCK_SIZE needs to be below 64KiB" +#endif +void bootblock_early_southbridge_init(void) { u16 reg16; pci_devfn_t dev; |