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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-28 15:11:56 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-28 15:11:56 +0000 |
| commit | 83a1dd850b9f61929a2db17a9429d3d193e34bfb (patch) | |
| tree | c3f0ab1329b7a882fccf8553842961f57b556c1b /src/southbridge/intel/i82371eb | |
| parent | f733d4754438f7289dd84d19871c7fe0a322801e (diff) | |
| download | coreboot-83a1dd850b9f61929a2db17a9429d3d193e34bfb.tar.xz | |
drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be looking for.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82371eb')
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index f105571380..cb4356ef8a 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); |