summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82371eb
diff options
context:
space:
mode:
authorMartin Roth <martinroth@google.com>2017-06-24 21:29:38 -0600
committerMartin Roth <martinroth@google.com>2017-07-16 19:22:18 +0000
commit7a1a3ad2ce3403f0379b72d30360e2bed02e9c26 (patch)
tree0db32f6a8f2349b5ce269996f3246b13fec9d5af /src/southbridge/intel/i82371eb
parent9fa8ebe1a41fab33badfa4745708e1ad237e8a34 (diff)
downloadcoreboot-7a1a3ad2ce3403f0379b72d30360e2bed02e9c26.tar.xz
southbridge/intel: add IS_ENABLED() around Kconfig symbol references
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82371eb')
-rw-r--r--src/southbridge/intel/i82371eb/isa.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index bd0e964378..2bab05cb15 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -28,7 +28,7 @@
#endif
#include "i82371eb.h"
-#if CONFIG_IOAPIC
+#if IS_ENABLED(CONFIG_IOAPIC)
static void enable_intel_82093aa_ioapic(void)
{
u16 reg16;
@@ -84,7 +84,7 @@ static void isa_init(struct device *dev)
/* Initialize ISA DMA. */
isa_dma_init();
-#if CONFIG_IOAPIC
+#if IS_ENABLED(CONFIG_IOAPIC)
/*
* Unlike most other southbridges the 82371EB doesn't have a built-in
* IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
@@ -115,7 +115,7 @@ static void sb_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
IORESOURCE_RESERVE;
-#if CONFIG_IOAPIC
+#if IS_ENABLED(CONFIG_IOAPIC)
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;