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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-28 14:37:06 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-28 14:37:06 +0000 |
| commit | 861f96403777c8f4475ca94613c5142075dd0cdf (patch) | |
| tree | 42d15ba06ada33c66f4654dd27f7d84e70a7aeca /src/southbridge/intel/i82371eb | |
| parent | f5a6fd253c3d289bd70917504f59255038d476a2 (diff) | |
| download | coreboot-861f96403777c8f4475ca94613c5142075dd0cdf.tar.xz | |
Lower the RAM init delays we use on the Intel 440BX.
As per JEDEC, we should wait 200us until voltages and clocks are stable.
Then apply NOPs for 200 clock cycles (for simplicity we use 200us here).
All other delays are so low that we get away with just waiting 1us.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82371eb')
0 files changed, 0 insertions, 0 deletions