diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-10-04 23:50:06 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-10-04 23:50:06 +0000 |
| commit | 90950925c79b4d0b48c3d9dfc1e3de6a67212a97 (patch) | |
| tree | a608e123d6def08edeeaa16075a8fe6fbf2bdeec /src/southbridge/intel/i82371eb | |
| parent | 24796fd364176ce8bb4f4eb727e0ba2ece188c08 (diff) | |
| download | coreboot-90950925c79b4d0b48c3d9dfc1e3de6a67212a97.tar.xz | |
The new CBFS based build system requires the whole ROM to be accessible
in very early stages, otherwise the boot may hang like this because
the CBFS headers cannot be found/accessed:
Uncompressing coreboot to RAM.
Jumping to image.
Check CBFS header at fffedfe0
magic is ffffffff
ERROR: No valid CBFS header found!
CBFS: Could not find file fallback/coreboot_ram
Jumping to image.
This patch enables full ROM access on all 440BX boards right after the
serial init (and before CBFS headers are parsed).
Build-tested and runtime-tested on ASUS P2B-F.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82371eb')
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb_enable_rom.c | 35 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb_isa.c | 8 |
2 files changed, 35 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c new file mode 100644 index 0000000000..5b12e462be --- /dev/null +++ b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "i82371eb.h" + +static void i82371eb_enable_rom(device_t dev) +{ + u16 reg16; + + /* Enable access to the whole ROM, disable ROM write access. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= LOWER_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE_1MB; + reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ + pci_write_config16(dev, XBCS, reg16); +} diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c index a521d86bb0..6a8de8d80e 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_isa.c +++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c @@ -35,14 +35,6 @@ static void isa_init(struct device *dev) /* Initialize the real time clock (RTC). */ rtc_init(0); - /* Enable access to all BIOS regions. */ - reg16 = pci_read_config16(dev, XBCS); - reg16 |= LOWER_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE_1MB; - reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ - pci_write_config16(dev, XBCS, reg16); - /* * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) * bus, which is a subset of ISA. We select the full ISA bus here. |