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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-06 19:00:31 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-09 21:29:53 +0000 |
| commit | 7cdcc38f292d7a8ffd285d17c848e60e41eec759 (patch) | |
| tree | 13bba3b16f89d74367fdc043e10d707534a24525 /src/southbridge/intel/i82371eb | |
| parent | c528426b264c897b6c17ef14846afea3711042cb (diff) | |
| download | coreboot-7cdcc38f292d7a8ffd285d17c848e60e41eec759.tar.xz | |
sb/intel/common: Add smbus_host_reset()
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82371eb')
| -rw-r--r-- | src/southbridge/intel/i82371eb/early_smbus.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 4168a057ef..917a3b45f1 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -15,12 +15,11 @@ */ #include <stdint.h> -#include <arch/io.h> +#include <console/console.h> #include <device/pci_ops.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82371eb.h" @@ -47,8 +46,9 @@ void enable_smbus(void) reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16); - /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + smbus_host_reset(SMBUS_IO_BASE); + + printk(BIOS_DEBUG, "SMBus controller enabled\n"); } int smbus_read_byte(u8 device, u8 address) |