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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-02-26 17:24:41 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-02-26 23:38:49 +0100
commite614353194c712a40aa8444a530b2062876eabe3 (patch)
tree58dc3f6ed52af5312b278c0790e4f9a7a04783d1 /src/southbridge/intel/i82801ax
parentcf4ecfbe0183b633f362d88d9ebf18b6d846d3d2 (diff)
downloadcoreboot-e614353194c712a40aa8444a530b2062876eabe3.tar.xz
Unify setting 82801a/b/c/d IOAPIC ID
Remove obscure local copy of writing the ioapic registers. Change-Id: I133e710639ff57c6a0ac925e30efce2ebc43b856 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801ax')
-rw-r--r--src/southbridge/intel/i82801ax/Kconfig1
-rw-r--r--src/southbridge/intel/i82801ax/lpc.c39
2 files changed, 22 insertions, 18 deletions
diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig
index 70734a7a15..71ae0163c2 100644
--- a/src/southbridge/intel/i82801ax/Kconfig
+++ b/src/southbridge/intel/i82801ax/Kconfig
@@ -19,6 +19,7 @@
config SOUTHBRIDGE_INTEL_I82801AX
bool
+ select IOAPIC
select HAVE_HARD_RESET
select USE_WATCHDOG_ON_BOOT
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index c9404ed3c0..1d296f414d 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -70,17 +70,30 @@ typedef struct southbridge_intel_i82801ax_config config_t;
* Use the defined IRQ values above or set mainboard
* specific IRQ values in your devicetree.cb.
*/
-static void i82801ax_enable_apic(struct device *dev)
-{
- u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR;
- volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+/**
+ * Enable ACPI I/O range.
+ *
+ * @param dev PCI device with ACPI and PM BAR's
+ */
+static void i82801ax_enable_acpi(struct device *dev)
+{
/* Set ACPI base address (I/O space). */
pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
/* Enable ACPI I/O range decode and ACPI power management. */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+}
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void i82801ax_enable_ioapic(struct device *dev)
+{
+ u32 reg32;
reg32 = pci_read_config32(dev, GEN_CNTL);
reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
@@ -90,18 +103,7 @@ static void i82801ax_enable_apic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- *ioapic_index = 0;
- *ioapic_data = (1 << 25);
-
- *ioapic_index = 0;
- reg32 = *ioapic_data;
- printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
- if (reg32 != (1 << 25))
- die("APIC Error\n");
-
- /* TODO: From i82801ca, needed/useful on other ICH? */
- *ioapic_index = 3; /* Select Boot Configuration register. */
- *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+ set_ioapic_id(IO_APIC_ADDR, 0x02);
}
static void i82801ax_enable_serial_irqs(struct device *dev)
@@ -219,8 +221,9 @@ static void lpc_init(struct device *dev)
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ i82801ax_enable_acpi(dev);
/* IO APIC initialization. */
- i82801ax_enable_apic(dev);
+ i82801ax_enable_ioapic(dev);
i82801ax_enable_serial_irqs(dev);