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authorPatrick Georgi <patrick@georgi-clan.de>2012-10-05 21:54:38 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2012-10-08 21:23:08 +0200
commit9aeb69447d3839675b2cac51c3e95a4724fd9b0d (patch)
treed9b1cc7483a51ab340d6d9fae78a30e562f99767 /src/southbridge/intel/i82801ax
parentec2c18ee6068ef6adf6f5be437d7047c91773654 (diff)
downloadcoreboot-9aeb69447d3839675b2cac51c3e95a4724fd9b0d.tar.xz
hpet: common ACPI generation
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/i82801ax')
-rw-r--r--src/southbridge/intel/i82801ax/i82801ax.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h
index bd192e019e..186a917975 100644
--- a/src/southbridge/intel/i82801ax/i82801ax.h
+++ b/src/southbridge/intel/i82801ax/i82801ax.h
@@ -33,7 +33,6 @@ int smbus_read_byte(u8 device, u8 address);
#define SMBUS_IO_BASE 0x0f00
#define PMBASE_ADDR 0x0400
-#define HPET_ADDR 0xfed00000
#define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64